During the design process of a new electronic device, such as a new semiconductor device, a designer usually performs a simulation of the real-time performance of the device. Such simulations may e.g. be performed pre- or post-layout of the semiconductor device. During the simulation, the performance of the designed device is tested against one or more of test scenarios by reporting reliability warnings and errors during quasi-stationary (DC) or transient simulations. Such warnings and errors may, for example, be issued by tools for detecting safe operating area (SOA) warnings and errors, errors due to electromigration (EM), errors due to electrostatic discharge (ESD), etc. The reported warnings and errors may be written into a log file which can be checked by the designer by inspection of all entries in the log file. In inspecting the log file, the designer evaluates all reported warnings and errors, uses a statistical analysis of the reported errors and warning, and/or uses some graphical representation indicating the positions of errors and warnings on the device design. However, when designers find such reliability warnings during pre- or post-layout simulation, it may be difficult or even impossible to assess how critical the warnings and errors are, and where to focus attention in adapting the design to overcome the violations. Often, there are too many warnings and errors produced by reliability checks, making it difficult for the designer to review and address all warnings and errors and having a risk that the designer overlooks a critical one. Further, warnings and errors may be due to non-critical transients or may have been introduced as a simulation artefact by the simulator and hence may not be relevant for the actual device, while still requiring attention from the designer.